The present invention relates to a semiconductor integrated circuit designed for testability, and the object is to reduce the power consumption of the test components thereof especially during the normal operation.
Among conventional semiconductor circuits, one of the most common ways of inserting a test circuit is the scan test method (refer to the non-patent document 1). FIG. 2(A) is a view of a circuit diagram illustrating a logic circuit (a combinational logic circuit) not including a test function. Since the logic circuit thereof cannot easily detect a malfunction inside the circuit, a component is added thereto so that a test scan can be done, shown in FIG. 2(B). In other words, a multiplexer MPX0-MPX2 is inserted to a preceding stage of a flip-flop FF0-FF2 of a component of the combinational circuit so that a path P0-P2 being used exclusively for a test and being different from a normal path can be composed. Then, setting a value of the flip-flop and reading the value thereof can be done easily, and subsequently a defect of the combinational circuit comprising the flip-flop in the production line can be detected. At the same time, a part of the test-only path (a path P0, P1 shown in FIG. 2(B)) is branched from the primary path of the flip-flop and is inputted to a multiplexer at the input stage of the flip-flop at the subsequent stage.
Recently, since a difficulty of test in large scale logic circuit has been increasing exponentially, the test can not be done without the scan test function thereof. Subsequently, the above mentioned scan test function has to be introduced, even though many circuit overheads are introduced to the part other than the primary circuitry and causes increasing of the power consumption thereof.
[Non-patent document 1] The special topic 2 of the March 2002 edition of homepage PR Magazine issued by Mentor Graphic Japan Co., Ltd.: What's DFTJ. URL:http//www.mentor.co.jp/N-V/02-03/TOPIC2.html.
While, in the case of a large scale integrated circuit (Ultra LSI), the request for low power consumption is very high. Consequently, even when a test scan function is introduced, the increase of power consumption should be minimized. However, with the scan-test introduced circuit configuration shown in FIG. 2(B), the reducing of power consumption thereof is not enough.
Since the test-only path P0-P2 shown in FIG. 2(B) is configured by branching the output path of the flip-flop FF0-FF2, the abovementioned path is driven during the normal operation not test operation even though the path is isolated by the selector at the subsequent stage and then operating power consumption exists.
Furthermore, by development of semiconductor manufacturing technology, finer pattern can be available to realize larger scale integrated circuit. At the same time, capacitance in wiring therein increases and delay time therein depends on the real layout thereof. Consequently, many delay circuits (for example, inverters) may be inserted to the test-only path between the flip-flops to adjust the timing to a logic circuit under a test. In the above case, the test-only path is driven even during the normal operation not test operation, causing the operating power consumption problem. Since the power consumption in the delay circuits (for example, inverters) is not small, the total power consumption is very large.
Most logic semiconductor integrated circuits are often fabricated with CMOS. The multi-stage delay circuit (for example, inverter) inserted to test-only path thereof is fabricated with CMOS, too. The recent CMOS technology arises some leak current, however, causing a problem of the non-operating power consumption of the test-only circuit during the normal operation not test operation.
Although the scan test is done once or several times during a certain period of the inspection for shipment, the normal operation is frequently conducted and then the power consumption during the normal operation is a big issue.
For the above-mentioned reason, a semiconductor integrated circuit that can prevent causes of the problem of the power consumption during normal operation thereof is being highly demanded
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved relay device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure